PEB2256HT datasheet(416/490 Pages) INFINEON

416 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

416

2002-08-27

Some of these alarm indications are simulated only if the FALC56 is configured in the

appropriate mode. At simulation steps 0, 3, 4, and 7 pending status flags are reset

automatically and clearing of the error counters and interrupt status registers ISR(5:0)

should be done. Incrementing the simulation counter should not be done at time intervals

shorter than 1.5 ms (F4, F12, F72) or 3 ms (ESF). Otherwise, reactions of initiated

simulations might occur at later steps. Control bit FMR0.SIM has to be held stable at high

or low level for at least one receive clock period before changing it again.

Framing Error Counter (Read)

FE(15:0)

Framing Errors

This 16-bit counter is incremented when incorrect FT and FS-bits in

F4, F12 and F72 format or incorrect FAS-bits in ESF format are

received.

Framing errors are counted during synchronous state only (but even

if multiframe synchronous state is not reached yet). The error counter

does not roll over.

During alarm simulation, the counter is incremented twice.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DFEC has

to be set. With the rising edge of this bit updating the buffer is stopped

and the error counter is reset. Bit DEC.DFEC is automatically reset

with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

FECL

FE7

FE0

(50)

FECH

FE15

FE8

(51)

PEB2256HT Datasheet(PDF) 416 Page - Infineon Technologies AG