PEB2256HT datasheet(421/490 Pages) INFINEON

421 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

421

2002-08-27

COFA Event Counter (Read)

COE(7:2)

Multiframe Counter

If GCR.ECMC = 1 this 6 bit counter increments with each multiframe

period in the asynchronous state FRS0.LFA/LMFA = 1. The error

counter does not roll over.

COE(1:0)

Change of Frame Alignment Counter

If GCR.ECMC = 1 this 2 bit counter increments with each detected

change of frame/multiframe alignment. The error counter does not roll

over.

During alarm simulation, the counter is incremented once per

multiframe.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the event counter bit DEC.DCOEC

has to be set. With the rising edge of this bit updating the buffer is

stopped and the error counter is reset. Bit DEC.DCOEC is

automatically reset with reading the error counter high byte on

address 5B

H. Data read on 5BH is not defined.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

COEC

COE7

COE2

COE1

COE0

(5A)

PEB2256HT Datasheet(PDF) 421 Page - Infineon Technologies AG