PEB2256HT datasheet(423/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

423

2002-08-27

Receive DL-Bit Register 3 (Read)

RDL3(7:0)

Receive DL-Bit

Only valid if F72 format is enabled.

The received DL-Bits are shifted into this register. RDL30 is received

in frame 58 and RDL37 in frame 72, if F72 format is enabled.

This register is updated with every receive multiframe begin interrupt

ISR0.RMB.

Receive Signaling Pointer 1 (Read)

Value after reset: 00H

RS(8:1)C

Receive Signaling Register RS(8:1) Changed

A one in each bit position indicates that the received signaling data in

the corresponding RS(8:1) registers are updated. Bit RS1C is the

pointer for register RS1, while RS8C points to RS8.

Receive Signaling Pointer 2 (Read)

Value after reset: 00H

RS(12:0)C

Receive Signaling Register RS(12:9) Changed

A one in each bit position indicates that the received signaling data in

the corresponding RS(12:9) registers are updated. Bit RS9C is the

pointer for register RS9, while RS12C points to RS12

RDL3

RDL37

RDL36

RDL35

RDL34

RDL33

RDL32

RDL31

RDL30

(5E)

RSP1

RS8C

RS7C

RS6C

RS5C

RS4C

RS3C

RS2C

RS1C

(62)

RSP2

RS12C

RS11C

RS10C

RS9C

(63)

PEB2256HT Datasheet(PDF) 423 Page - Infineon Technologies AG

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