PEB2256HT datasheet(430/490 Pages) INFINEON

430 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

430

2002-08-27

Interrupt Status Register 1 (Read)

All bits are reset when ISR1 is read.

If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are masked by

INT, nor are visible in register GIS.

CASE

Transmit CAS Register Empty

In ESF format this bit is set with the beginning of a transmitted

multiframe related to the internal transmitter timing. In F12 and F72

format this interrupt occurs every 24 frames to inform the user that

new bit robbing data may be written to the XS(12:1) registers. This

interrupt is generated only if the serial signaling access on the system

highway is not enabled.

RDO

Receive Data Overflow - HDLC Channel 1

This interrupt status indicates that the CPU did not respond fast

enough to an RPF or RME interrupt and that data in RFIFO has been

lost. Even when this interrupt status is generated, the frame continues

to be received when space in the RFIFO is available again.

Note: Whereas the bit RSIS.RDO in the frame status byte indicates

whether an overflow occurred when receiving the frame

currently accessed in the RFIFO, the ISR1.RDO interrupt status

is generated as soon as an overflow occurs and does not

necessarily pertain to the frame currently accessed by the

processor.

ALLS

All Sent - HDLC Channel 1

This bit is set if the last bit of the current frame has been sent

completely and XFIFO is empty. This bit is valid in HDLC mode only.

XDU

Transmit Data Underrun - HDLC Channel 1

Transmitted frame was terminated with an abort sequence because

no data was available for transmission in XFIFO and no XME was

issued.

Note: Transmitter and XFIFO are reset and deactivated if this

condition occurs. They are reactivated not before this interrupt

status register has been read. Thus, XDU should not be

masked by register IMR1.

ISR1

CASE

RDO

ALLS

XDU

XMB

SUEX

XLSC

XPR

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