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PEB2256HT Datasheet(PDF) 433 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 433 Page - Infineon Technologies AG |
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433 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 433 2002-08-27 Interrupt Status Register 3 (Read) All bits are reset when ISR3 is read. If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are masked by register IMR3. However, these masked interrupt statuses neither generate a signal on INT, nor are visible in register GIS. ES Errored Second This bit is set if at least one enabled interrupt source by ESM is set during the time interval of one second. Interrupt sources of ESM register: LFA = Loss of frame alignment detected FER = Framing error received CER = CRC error received AIS = Alarm indication signal (blue alarm) LOS = Loss-of-signal (red alarm) CVE = Code violation detected SLIP = Transmit slip or receive slip positive/negative detected SEC Second Timer The internal one-second timer has expired. The timer is derived from clock RCLK. LLBSC Line Loop-Back Status Change/PRBS Status Change Depending on bit LCR1.EPRM the source of this interrupt status changed: LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB deactivate signal is detected over a period of 33,16 ms with a bit error rate less than 10 -2. The LLBSC bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 10 -2. The actual detection status can be read from the FRS1.LLBAD and FRS1.LLBDD, respectively. PRBS Status Change LCR1.EPRM = 1: With any change of state of the PRBS synchronizer this bit is set. The current status of the PRBS synchronizer is indicated in FRS1.LLBAD. 70 ISR3 ES SEC LLBSC RSN RSP (6B) |
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