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PEB2256HT Datasheet(PDF) 437 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 437 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
437
2002-08-27
RDO3
Receive Data Overflow - HDLC Channel 3
This interrupt status indicates that the CPU did not respond fast
enough to an RPF3 or RME3 interrupt and that data in RFIFO3 has
been lost. Even when this interrupt status is generated, the frame
continues to be received when space in the RFIFO3 is available
again.
Note: Whereas the bit RSIS3.RDO3 in the frame status byte
indicates whether an overflow occurred when receiving the
frame currently accessed in the RFIFO3, the ISR5.RDO3
interrupt status is generated as soon as an overflow occurs
and does not necessarily pertain to the frame currently
accessed by the processor.
ALLS3
All Sent - HDLC Channel 3
This bit is set if the last bit of the current frame has been sent
completely and XFIFO3 is empty. This bit is valid in HDLC mode only.
XDU3
Transmit Data Underrun - HDLC Channel 3
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO3 and no XME3 was
issued.
Note: Transmitter and XFIFO3 are reset and deactivated if this
condition occurs. They are reactivated not before this interrupt
status register has been read. Thus, XDU3 should not be
masked via register IMR5.
RPF3
Receive Pool Full - HDLC Channel 3
32 bytes of a frame have arrived in the receive FIFO3. The frame is
not yet completely received.
Global Interrupt Status Register (Read)
Value after reset: 00
H
This status register points to pending interrupts sourced by ISR(5:0).
70
GIS
ISR5ISR4ISR3ISR2ISR1ISR0
(6E)



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