PEB2256HT datasheet(441/490 Pages) INFINEON

441 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

441

2002-08-27

• MDS2(2:0) = 010 (8 bit Address),

RCRC2=0 : 3 bytes; RCRC2=1 : 2 or 3 bytes

Note: Shorter frames are not reported.

RDO2

Receive Data Overflow - HDLC Channel 2

A data overflow has occurred during reception of the frame.

Additionally, an interrupt can be generated

(refer to ISR4.RDO2/IMR4.RDO2).

CRC162

CRC16 Compare/Check - HDLC Channel 2

= CRC check failed; received frame contains errors.

= CRC check o.k.; received frame is error-free.

RAB2

Receive Message Aborted - HDLC Channel 2

This bit is set, if more than 5 contiguous 1-bits are detected.

HA12, HA02

High Byte Address Compare - HDLC Channel 2

Significant only if 2-byte address mode is selected.

In operating modes which provide high byte address recognition, the

FALC

® compares the high byte of a 2-byte address with the contents

of two individually programmable registers (RAH1, RAH2) and the

fixed values FE

H and FCH (broadcast address).

Depending on the result of this comparison, the following bit

combinations are possible:

00 = RAH2 has been recognized

01 = Broadcast address has been recognized

10 = RAH1 has been recognized C/R=0 (bit 1)

11 = RAH1 has been recognized C/R=1 (bit 1)

Note: If RAH1, RAH2 contain identical values, a match is indicated by

"10" or "11".

PEB2256HT Datasheet(PDF) 441 Page - Infineon Technologies AG