PEB2256HT datasheet(442/490 Pages) INFINEON

442 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

442

2002-08-27

LA2

Low Byte Address Compare - HDLC Channel 2

Significant in HDLC modes only.

The low byte address of a 2-byte address field, or the single address

byte of a 1-byte address field is compared with two registers. (RAL1,

RAL2).

= RAL2 has been recognized

= RAL1 has been recognized

Signaling Status Register 3 (Read)

Value after reset: 00

XDOV3

Transmit Data Overflow - HDLC Channel 3

More than 32 bytes have been written to the XFIFO3.

This bit is reset

– by a transmitter reset command XRES or

– when all bytes in the accessible half of the XFIFO3 have been

moved in the inaccessible half.

XFW3

Transmit FIFO Write Enable - HDLC Channel 3

Data can be written to the XFIFO3.

XREP3

Transmission Repeat - HDLC Channel 3

Status indication of CMDR3.XREP3.

RLI3

Receive Line Inactive - HDLC Channel 3

Neither flags as interframe time fill nor frames are received via the

signaling time slot.

CEC3

Command Executing - HDLC Channel 3

= No command is currently executed, the CMDR4 register can be

written to.

= A command (written previously to CMDR4) is currently

executed, no further command can be temporarily written in CMDR4

Note: CEC3 will be active at most 2.5 periods of the current system

data rate.

SIS3

XDOV3

XFW3

XREP3

RLI3

CEC3

(9A)

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