PEB2256HT datasheet(443/490 Pages) INFINEON

443 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

443

2002-08-27

Receive Signaling Status Register 3 (Read)

Value after reset: 00

RSIS3 relates to the last received HDLC channel 3 frame; it is copied into RFIFO3 when

end-of-frame is recognized (last byte of each stored frame).

VFR3

Valid Frame - HDLC Channel 3

Determines whether a valid frame has been received.

Valid

Invalid

An invalid frame is either

– a frame which is not an integer number of 8 bits (n

×8 bits) in length

(e.g. 25 bits), or

– a frame which is too short taking into account the operation mode

selected via MODE3 (MDS3(2:0)) and the selection of receive CRC

ON/OFF (CCR4.RCRC3) as follows:

• MDS3(2:0)=011 (16 bit Address),

RCRC3=0: 4 bytes; RCRC3=1: 3 or 4 bytes

• MDS3(2:0)=010 (8 bit Address),

RCRC3=0: 3 bytes; RCRC3=1: 2 or 3 bytes

Note: Shorter frames are not reported.

RDO3

Receive Data Overflow - HDLC Channel 3

A data overflow has occurred during reception of the frame.

Additionally, an interrupt can be generated

(refer to ISR5.RDO3/IMR5.RDO3).

CRC163

CRC16 Compare/Check - HDLC Channel 3

= CRC check failed; received frame contains errors.

= CRC check o.k.; received frame is error-free.

RAB3

Receive Message Aborted - HDLC Channel 3

This bit is set, if more than 5 contiguous 1-bits are detected.

RSIS3

VFR3

RDO3

CRC163

RAB3

HA13

HA03

LA3

(9B)

PEB2256HT Datasheet(PDF) 443 Page - Infineon Technologies AG

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