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PEB2256HT Datasheet(PDF) 460 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 460 Page - Infineon Technologies AG |
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460 / 490 page ![]() FALC56 V1.2 PEB 2256 Electrical Characteristics Data Sheet 460 2002-08-27 11.4.6 System Interface Figure 92 RCLK, RFSP Output Timing Table 76 RCLK, RFSP Timing Parameter Values No. Parameter Limit Values Unit min. typ. max. 1 RCLK period E1 (2.048 MHz) 488 ns RCLK period E1 (2.048 MHz × 4) 122 ns RCLK period T1/J1 (1.544 MHz) 648 ns RCLK period T1/J1 (1.544 MHz × 4) 162 ns 2 RCLK pulse high 40 60 % 3 RCLK pulse low 40 60 % 4RFSP delay 80 ns F0009 data valid RCLK RFSP (output) Note: active edge can be programmed to be positive or negative (only negative edge timing shown here); valid only, if RCLK id derived from DPLL (not, if RCLK jitter is attenuated) 1 2 3 4 |
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