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PEB2256HT Datasheet(PDF) 111 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 111 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description E1
Data Sheet
111
2002-08-27
4.5.2.1
Transmit Offset Programming
The pulse length of SYPX is always the basic E1 bit width (488 ns), independent of the
selected system highway clock and data frequency.
SYPX Offset Calculation
T:
Time between beginning of SYPX pulse and beginning of next frame
(time slot 0, bit 0), measured in number of SCLKX clock intervals
maximum delay: T
max =(256 × SC/SD)-1
SD:
Basic data rate; 2.048 Mbit/s
SC:
System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz
X:
Programming value to be written to registers XC0 and XC1 (see page 237).
0
≤ T ≤ 4:
X = 4 - T
5
≤ T ≤ T
max: X = 256 × SC/SD - T + 4



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