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PEB2256HT Datasheet(PDF) 115 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 115 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description E1
Data Sheet
115
2002-08-27
4.6.3
Payload Loop-Back
To perform an effective circuit test a payload loop is implemented. The payload loop-
back (FMR2.PLB) loops the data stream from the receiver section back to transmitter
section. The looped data passes the complete receiver including the wander and jitter
compensation in the receive elastic store and is output on pin RDO. Instead of the data
an AIS signal (FMR2.SAIS) can be sent to the system interface.
The framing bits, CRC4 and spare bits are not looped, if XSP.TT0 = 0. They are
generated by the FALC56 transmitter. If the PLB is enabled the transmitter and the data
on pins XL1/2 or XDOP/XDON are clocked with SCLKR instead of SCLKX. If
XSP.TT0 = 1 the received time slot 0 is sent back transparently to the line interface. Data
on the following pins is ignored: XDI, XSIG, SCLKX, SYPX and XMFS. All the received
data is processed normally.
Figure 38
Payload Loop (E1)
ITS09748
Clock +
Data
Rec.
Framer
Elast.
Store
Trans.
Framer
RDO
XDI
RCLK
RL1
RL2
XL1
XL2
Recovery
SCLKX
SCLKR
MUX
AIS-GEN
Elast.
Store



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