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PEB2256HT Datasheet(PDF) 168 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 168 Page - Infineon Technologies AG |
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168 / 490 page ![]() FALC56 V1.2 PEB 2256 Functional Description T1/J1 Data Sheet 168 2002-08-27 5.5.1.1 Receive Offset Programming Depending on the selection of the synchronization signals (SYPR or RFM), different calculation formulas are used to define the position of the synchronization pulses. These formulas are given below, see Figure 56 to Figure 59 for explanation. The pulse length of SYPR and RFM is always the basic T1/J1 bit width (648 ns) in 1.544-MHz mode or the E1 bit width (488 ns) in 2.048-MHz mode. This chapter describes the system highway operation in 1.544-MHz mode only. If the system highway is operated in 2.048-MHz mode, the description given in Chapter 4.5.1.1 on page 106 applies. SYPR Offset Calculation T: Time between beginning of SYPR pulse and beginning of next frame (time slot 0, bit 0), measured in number of SCLKR clock intervals maximum delay: T max =(193 × SC/SD)-1 SD: Basic data rate; 1.544 Mbit/s SC: System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz X: Programming value to be written to registers RC0 and RC1 (see page 359). 0 ≤ T ≤ 4: X = 4 - T + (7 × SC/SD) 5 ≤ T ≤ T max: X = (200 × SC/SD) + 4 - T RFM Offset Calculation MP: Marker position of RFM, counting in SCLKR clock cycles (0 = F-bit) SC = 1.544 MHz: 0 ≤ MP ≤ 192 SC = 3.088 MHz: 0 ≤ MP ≤ 385 SC = 6.176 MHz: 0 ≤ MP ≤ 771 SC = 12.352 MHz: 0 ≤ MP ≤ 1543 SD: Basic data rate; 1.544 Mbit/s SC: System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz X: Programming value to be written to registers RC0 and RC1 (see page 359). 0 ≤ MP ≤ 193 × (SC/SD) - 3: X = MP + 2 + (7 × SC/SD) 193 × (SC/SD)-2 ≤ MP ≤ 193 × (SC/SD) - 1: X = MP + 2 - (186 × SC/SD) |
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