Electronic Components Datasheet Search
  English  ▼

X  

PEB2256HT Datasheet(PDF) 168 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 168 Page - Infineon Technologies AG

Back Button PEB2256HT Datasheet HTML 164Page - Infineon Technologies AG PEB2256HT Datasheet HTML 165Page - Infineon Technologies AG PEB2256HT Datasheet HTML 166Page - Infineon Technologies AG PEB2256HT Datasheet HTML 167Page - Infineon Technologies AG PEB2256HT Datasheet HTML 168Page - Infineon Technologies AG PEB2256HT Datasheet HTML 169Page - Infineon Technologies AG PEB2256HT Datasheet HTML 170Page - Infineon Technologies AG PEB2256HT Datasheet HTML 171Page - Infineon Technologies AG PEB2256HT Datasheet HTML 172Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 168 / 490 page
background image
FALC56 V1.2
PEB 2256
Functional Description T1/J1
Data Sheet
168
2002-08-27
5.5.1.1
Receive Offset Programming
Depending on the selection of the synchronization signals (SYPR or RFM), different
calculation formulas are used to define the position of the synchronization pulses. These
formulas are given below, see Figure 56 to Figure 59 for explanation. The pulse length
of SYPR and RFM is always the basic T1/J1 bit width (648 ns) in 1.544-MHz mode or
the E1 bit width (488 ns) in 2.048-MHz mode.
This chapter describes the system highway operation in 1.544-MHz mode only. If the
system highway is operated in 2.048-MHz mode, the description given in
Chapter 4.5.1.1 on page 106 applies.
SYPR Offset Calculation
T:
Time between beginning of SYPR pulse and beginning of next frame
(time slot 0, bit 0), measured in number of SCLKR clock intervals
maximum delay: T
max =(193 × SC/SD)-1
SD:
Basic data rate; 1.544 Mbit/s
SC:
System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz
X:
Programming value to be written to registers RC0 and RC1 (see page 359).
0
≤ T ≤ 4:
X = 4 - T + (7
× SC/SD)
5
≤ T ≤ T
max: X = (200 × SC/SD) + 4 - T
RFM Offset Calculation
MP:
Marker position of RFM, counting in SCLKR clock cycles (0 = F-bit)
SC = 1.544 MHz:
0
≤ MP ≤ 192
SC = 3.088 MHz:
0
≤ MP ≤ 385
SC = 6.176 MHz:
0
≤ MP ≤ 771
SC = 12.352 MHz:
0
≤ MP ≤ 1543
SD:
Basic data rate; 1.544 Mbit/s
SC:
System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz
X:
Programming value to be written to registers RC0 and RC1 (see page 359).
0
≤ MP ≤ 193 × (SC/SD) - 3: X = MP + 2 + (7 × SC/SD)
193
× (SC/SD)-2 ≤ MP ≤ 193 × (SC/SD) - 1: X = MP + 2 - (186 × SC/SD)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com