PEB2256HT datasheet(172/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

172

2002-08-27

Figure 62

1.544 MHz Receive Signaling Highway (T1/J1)

5.5.2

Transmit System Interface (T1/J1)

Compared to the receive paths the inverse functions are performed for the transmit

direction.

The interface to the transmit system highway is realized by two data buses, one for the

data XDI and one for the signaling data XSIG. The time slot assignment is equivalent to

the receive direction. All unequipped (idle) time slots are ignored.

Latching of data is controlled by the system clock (SCLKX or SCLKR) and the

synchronization pulse (SYPX/XMFS) in combination with the programmed offset values

for the transmit time slot/clock slot counters XC1/0. The frequency of the working clock

2.048/4.096/8.192/16.384 MHz or 1.544/3.088/6.176/12.352 MHz for the transmit

system interface is programmable by SIC1.SSC1/0 and SIC2.SSC2. Refer also

Table 44.

The received bit stream on ports XDI and XSIG can be multiplexed internally on a time

slot basis, if enabled by SIC3.TTRF = 1. The data received on port XSIG can be sampled

if the transmit signaling marker XSIGM is active high. Data on port XDI is sampled if

XSIGM is low for the corresponding time slot. Programming the XSIGM marker is done

with registers TTR(4:1).

Note: XSIG is required in the last frame of a multiframe only and ignored in all other

frames.

F0134

A B C D

4 5 6 7

0 1 2 3 4 5 6 7

TS23

TS0

TS1

A B C D

0 1 2 3 4 5 6 7

TS23

RSIG

RDO

SCLKR

SYPR

125 µs

= Time slot offset (RC0, RC1)

F= FS/DL-bit

ABCD, ABAB

= Signaling bits for time slots 1...23

0 1 2 3 4 5 6 7

A B C D

ESF

F12

A B A B

RSIG

A B A B

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