GS1671 datasheet(37/130 Pages) SEMTECH

37 / 130 page

GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

37 of 130

4.9 Timing Signal Generator

The GS1671 has an internal timing signal generator which is used to generate digital

FVH timing reference signals, to detect and correct certain error conditions and

automatic video standard detection.

The timing signal generator is only operational in SMPTE mode (SMPTE_BYPASS =

HIGH).

The timing signal generator consists of a number of counters and comparators operating

at video pixel and video line rates. These counters maintain information about the total

line length, active line length, total number of lines per field/frame and total active lines

per field/frame for the received video standard.

It takes one video frame to obtain full synchronization to the received video standard.

NOTE: Both 8-bit and 10-bit TRS words are identified by the device. Once

synchronization has been achieved, the timing signal generator continues to monitor

the received TRS timing information to maintain synchronization.

The timing signal generator re-synchronizes all pixel and line based counters on every

received TRS ID. Note that for correct operation of the timing signal generator, the

SW_EN input pin must be set LOW, unless manual synchronous switching is enabled

(Section 4.9.1).

4.9.1 Manual Switch Line Lock Handling

The principle of switch line lock handling is that the switching of synchronous video

sources will only disturb the horizontal timing and alignment, whereas the vertical

timing remains in synchronization - i.e. switching between video sources of the same

format.

To account for the horizontal disturbance caused by a synchronous switch, the word

alignment block and timing signal generator automatically re-synchronizes to the new

timing immediately if the synchronous switch happens during the designated switch

line, as defined in SMPTE recommended practice RP168-2002.

The device samples the SW_EN pin on every PCLK cycle. When a Logic LOW to HIGH

transition on this pin is detected anywhere within the active line, the word alignment

block and timing signal generator re-synchronize immediately to the next TRS word.

This allows the system to force immediate lock on any line, if the switch point is

non-standard.

To ensure proper switch line lock handling, the SW_EN signal should be asserted HIGH

anywhere within the active portion of the line on which the switch has taken place, and

should be held HIGH for approximately one video line. After this time period, SW_EN

should be de-asserted. SW_EN should be held LOW during normal device operation.

NOTE: It is the rising edge of the SW_EN signal, which generates the switch line lock

re-synchronization. This edge must be in the active portion of the line containing the

video switch point.

GS1671 Datasheet(PDF) 37 Page - Semtech Corporation

GS1671 Datasheet(HTML) 37 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL