GS1671 datasheet(71/130 Pages) SEMTECH

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GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

71 of 130

Figure 4-34: ECC 24-bit Array and Examples

4.18.3 Audio Processing

4.18.3.1 Audio Clock Generation

For SD and HD audio, a single set of audio frequencies is generated for all audio

channels, using a Direct Digital Period Synthesizer (DDPS) to minimize jitter.

In SD mode, audio clocks are derived from the PCLK.

In HD mode, the input control for the DDPS is derived from the two embedded audio

clock phase words in the audio data packet corresponding to Group A. The audio clock

phase information used is taken from the first embedded audio packet in the HANC

space. With no embedded audio present, the device will not generate ACLK or WCLK.

The IGNORE_PHASE bit should be asserted in this case to ensure the proper AMCLK

frequency is generated.

The audio de-embedder also includes a Flywheel block to overcome any inconsistencies

in the embedded audio clock phase information.

If the audio phase data is not present in the audio data packets, or is incorrect, the

NO_PHASEA_DATA bit in the host interface is set and the clock will free-run based on

the detected video format, the PCLK and the M value. IGNORE_PHASE should be set

HIGH when NO_PHASEA_DATA is set. This does not occur automatically.

When the IGNORE_PHASE bit in the host interface is set HIGH, it is recommended that

the M value be programmed via the host interface. This can be done by setting the

FORCE_M bit HIGH, and programming the desired value into FORCE_MEQ1001. The

correct value can be obtained by reading the M bit from the Video Core Registers.

If the DDPS is locked to phase data and audio data packets are lost or corrupted, the

Clock Generator will flywheel for up to four audio data packets. If no valid audio data

packet with valid phase data is provided within this time, the Clock Generator will

free-run based on the video format, the PCLK and the M value.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

24-bit array

ADF ADF ADF DID DBN DC

CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Errors corrected

ADF ADF ADF DID DBN DC

CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Errors detected but not corrected

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