GS1671 datasheet(82/130 Pages) SEMTECH

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GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

82 of 130

4.20 Host Interface Register Maps

NOTE: The GS1671 only accepts write/read commands to/from the Audio Register

Maps when the audio core is locked to the incoming video data rate. The Video Register

Map is always active, whether valid serial input data is present or not.

4.20.1 Video Core Registers

Table 4-28: Video Core Configuration and Status Registers

Address

Bit Name

Bit

Description

R/W

Default

000h

IOPROC_1

RSVD

Reserved.

TRS_WORD_REMAP_DS1

_DISABLE

Disables 8-bit TRS word remapping

for HD and SD inputs.

R/W

RSVD

Reserved.

R/W

EDH_FLAG_UPDATE

_MASK

Disables updating of EDH error

flags.

R/W

EDH_CRC_INS_MASK11

Disables EDH_CRC error correction

and insertion.

R/W

H_CONFIG

Selects the H blanking indication:

0: Active line blanking - the H

output is HIGH for all the

horizontal blanking period,

including the EAV and SAV TRS

words.

1: TRS based blanking - the H

output is set HIGH for the entire

horizontal blanking period as

indicated by the H bit in the

received TRS signals.

This signal is only valid when

TIM_861 is set to '0' (via pin or host

interface).

R/W

ANC_DATA_EXT_MASK9

Disables ancillary data extraction

FIFO.

R/W

AUD_EXT_MASK8

Disables audio extraction block.

R/W

TIM_861_PIN_DISABLE

Disable TIM_861 pin control when

set to '1', and use TIMING_861 bit

instead.

R/W

TIMING_861

6Selects the output timing reference

format: 0 = Digital FVH timing

output; 1 = CEA-861 timing output.

R/W

RSVD

Reserved.

R/W

ILLEGAL_WORD_REMAP

_DS1_MASK

4Disables illegal word remapping

for HD and SD inputs.

R/W

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