GS1671 datasheet(59/130 Pages) SEMTECH

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GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

59 of 130

By default (at power up or after system reset), all of the IOPROC_DISABLE register bits

are LOW, enabling all of the processing features.

To disable an individual processing feature, set the corresponding IOPROC_DISABLE bit

HIGH in the IOPROC_DISABLE register.

4.17.1 TRS Correction & Insertion

When TRS Error Correction and Insertion is enabled, the GS1671 generates and

overwrites TRS code words as required.

TRS Word Generation and Insertion is performed using the timing generated by the

Timing Signal Generator, providing an element of noise immunity over using just the

received TRS information.

This feature is enabled when the IOPROC_EN/DIS pin is HIGH and the

TRS_INS_DISABLE bit in the IOPROC_DISABLE register is set LOW.

NOTE: Inserted TRS code words are always 10-bit compliant, irrespective of the bit

depth of the incoming video stream.

4.17.2 Line Based CRC Correction & Insertion

When CRC Error Correction and Insertion is enabled, the GS1671 generates and inserts

line based CRC words into both the Y and C channels of the data stream.

Line based CRC word generation and insertion only occurs in HD mode, and is enabled

in when the IOPROC_EN/DIS pin is HIGH and the CRC_INS_DSX_MASK bit in the

IOPROC_X register is set LOW.

Table 4-14: IOPROC_DISABLE Register Bits

Processing Feature

IOPROC_DISABLE Register Bit

TRS error correction and insertion

TRS_INS

Y and C line based CRC error correction

CRC_INS

Y and C line number error correction

LNUM_INS

Ancillary data check sum correction

ANC_CHECKSUM_INSERTION

EDH CRC error correction

EDH_CRC_INS

Illegal code re-mapping

ILLEGAL_WORD_REMAP

H timing signal configuration

H_CONFIG

Update EDH Flags

EDH_FLAG_UPDATE_MASK

Audio Data Extraction

AUDIO_SEL

Ancillary Data Extraction

ANC_DATA_EXT

Audio Extraction

AUD_EXT

Regeneration of 352M packets

REGEN_352M

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