GS1671 datasheet(52/130 Pages) SEMTECH

52 / 130 page

GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

52 of 130

One set of flags is provided for both fields 1 and 2. The field 1 flag data is overwritten by

the field 2 flag data.

When EDH packets are not detected, the UES flags in the EDH_FLAG_OUT register are

set HIGH to signify that the received signal does not support Error Detection and

Handling. In addition, the EDH_DETECT bit is set LOW. These flags are set regardless of

the setting of the EDH_FLAG_UPDATE_MASK bit.

EDH_FLAG_OUT and EDH_FLAG_IN may be read via the host interface at any time

during the received frame except on the lines defined in SMPTE RP165, when these flags

are updated.

The GS1671 indicates the CRC validity for both active picture and full field CRCs. The

AP_CRC_V bit in the host interface indicates the active picture CRC validity, and the

FF_CRC_V bit indicates the full field CRC validity. When EDH_DETECT = LOW, these

bits are cleared.

The EDH_FLAG_OUT and EDH_FLAG_IN register values remain set until overwritten by

the decoded flags in the next received EDH packet. When an EDH packet is not detected

during vertical blanking, the flag registers are cleared at the end of the vertical blanking

period.

4.15 Video Signal Error Detection & Indication

The GS1671 includes a number of video signal error detection functions. These are

provided to enhance operation of the device when operating in SMPTE mode

(SMPTE_BYPASS = HIGH). These features are not available in the other operating modes

of the device (i.e. when SMPTE_BYPASS = LOW).

Signal errors that can be detected include:

1. TRS errors.

2. HD line based CRC errors.

3. EDH errors.

4. HD line number errors.

5. Video standard errors.

The device maintains an ERROR_STAT_X register. Each error condition has a specific

flag in the ERROR_STAT_X register, which is set HIGH whenever an error condition is

detected.

An ERROR_MASK register is also provided, allowing the user to select which error

conditions are reported. Each bit of the ERROR_MASK register corresponds to a unique

error type.

Separate SD_AUDIO_ERROR_MASK and HD_AUDIO_ERROR_MASK registers for SD

and HD audio cores are also provided, allowing select error conditions to be reported.

Each bit of each ERROR_MASK register corresponds to a unique error type.

By default (at power up or after system reset), all bits of the ERROR_MASK registers are

zero, enabling all errors to be reported. Individual error detection may be disabled by

setting the corresponding bit HIGH in the mask registers.

GS1671 Datasheet(PDF) 52 Page - Semtech Corporation

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