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Z80 Datasheet(PDF) 164 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 164 Page - Zilog, Inc. |
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164 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Figure 56. Connecting DMA to Demultiplexed Address/Data Buses Many processors encode their control signals, as does the Z80’s M1, MREQ,IORQ,RD,and WR, into status words that are often demultiplexed before they are distributed to memory, peripherals, and more. Link the DMA to these demultiplexed signals and take advantage of tristate decoders to float the outputs when the DMA is master. The DMA’s Z80-like control signals must usually be retimed to meet the requirements of the foreign buses. But the programmable timing feature of the DMA may well reduce the hardware costs incurred. Interrupt Request, Acknowledge, and Return When using the DMA with other processors, this area is the most chal- lenging because of the many methods of signaling, prioritizing, identifying, responding to, and returning from interrupts. Latched Address Bus CPU DMA Buffered Bidirectional Data Bus Multiplexed Address and Data Bus 3-Stage Latches |
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