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Z80 Datasheet(PDF) 165 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 165 Page - Zilog, Inc. |
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165 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Non-Z80 interrupt environments do not use the IEI and IEO signals, and often they use separate interrupt controllers to generate vectors, and handle acknowledgement and return in different ways, or not at all. Interrupt request is usually easy: active levels typically are low voltage, and there may be one or more separate interrupt request pins. Timing require- ments for interrupt requests are varied and may including pulse widths, latching, and more, and must be carefully examined. Priority of simultaneous or overlapping requests is handled in several ways: some processors (for example, the 8085) have multiple interrupt-request pins, some use daisy-chained priority schemes (as in the Z80), and several types of interrupt control ICs are available. Acknowledgement and identification methods vary too. Sometimes, several fixed memory locations correspond to different interrupt pins’ service routines. In other cases, the interrupting device identifies itself by putting a vector or instruction on the data bus for the CPU to read. Interrupt controllers often provide appropriate vectors to the CPU and distinguish between and prioritize multiple requests. The DMA has the built-in capa- bility of supplying an arbitrary vector byte when it detects a Z80 interrupt acknowledge (IORQ and M1 both active) and its IEI input is active (no higher-priority device is interrupting). Often, then, gating the M1,IORQ, and IEI pins appropriately can rule out using a separate interrupt controller. IORQ serves another function, too, therefore it must appear during CPU- DMA transfers and be available to signal I/O reads or writes in the active state. At the end of its service routine, the DMA anticipates the CPU fetching the RETI instruction (ED, 4D present on the data bus accompanied by M1). The DMA command RESET AND DISABLE INTERRUPTS is designed for this purpose in non-Z80 CPU environments. Alternatively, the RETI instructionmight be simulatedbyre-gatingM1 and programming the CPU to write to a phantom peripheral the bytes ED, 4D. The chip select for this nonexistent peripheral is used to simulate M1. SeeFigure57. |
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