Z80 datasheet(291/330 Pages) ZILOG

291 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

271

When End Of Frame Interrupt occurs, the

CPU performs

the following:

Detection of End-of-frame (flag)

causes Interrupt and deactivates the

Wait/Ready function. Residue codes

indicate the bit structure of the last

two bytes of the message that were

transferred to memory under DMA.

'error Reset' is issued to clear the

special condition. Abort Sequence is

detected when seven or more 1s occur

in the data stream.

• Exits DMA Mode (disables Wait/

Ready)

• Transfers RR1 to the CPU

• Checks the CRC error bit status and

residue codes

• Updates NR count

• Issues Error Reset Command to SIO

When Abort Sequence Detected Interrupt

occurs, the CPU performs the following:

• Transfers RR0 to the CPU

• Exits DMA Mode

• Issues the Reset External Status

Interrupt Command to the SIO

• Enters the Idle Mode

CPU is waiting for Abort Sequence to

terminate. Termination clears the

Break/Abort status bit and causes

interrupt. at this point, the program

proceeds to terminate this message.

When the second Abort Sequence

Interrupt occurs, the CPU performs the

following:

• Issues the Reset External Status

Interrupt Command to the SIO

Termination

Redefine Interrupt Modes, Sync Mode

and SDLC Modes, Disable Receive

Mode

Table 10. SDLC Receive Mode (Continued)

Function

Typical Program Steps

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