Z80 datasheet(297/330 Pages) ZILOG

297 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

277

The Reset Transmit CRC Generator command normally initializes the CRC

generator to 0s. If the SDLC mode is selected, this command initializes the

CRC generator to 1s. The Receive CRC checker is also initialized to 1s for

the SDLC mode.

Write Register 1

WR1 (Figure 115) contains the control bits for the various interrupt and

Wait/Ready modes.

External/Status Interrupt Enable (D0)

The External/Status Interrupt Enable allows interrupts to occur as a result of

transitions on the DCD,CTS,or SYNC inputs, as a result of a Break/Abort

Table 14. Reset Commands

CRC Reset

Code 1

CRC Reset

Code 0

Result

Null Code (no affect)

Reset Receive CRC Checker

Reset Transmit CRC Generator

Reset Tx Underrun/End of Message latch

Table15. WriteRegister1

Wait/Ready

Enable

Wait or Ready

Function

Wait/Ready on

Receive Transmit

Receive Interrupt

Mode 1

Receive Interrupt

Mode 0

Status Affects

Vector

Transmit Interrupt

Enable

External Interrupts

Enable

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