Z80 datasheet(298/330 Pages) ZILOG

298 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

278

detection and termination, or at the beginning of CRC or sync character

transmission when the Transmit Underrun/EOM latch sets.

Transmitter Interrupt Enable (D1)

If enabled, interrupts occur whenever the transmitter buffer becomes empty.

Status Affects Vector (D2)

This bit is active in Channel B only. If this bit is not set, the fixed vector

programmed in WR2 is returned from an interrupt acknowledge sequence.

If this bit is set, the vector returned from an interrupt acknowledge is

variable. Table 16 describes the vector results. Table 17 describes the

Receive Interrupt modes.

Receive Interrupt Modes 0 and 1 (D3 and D4)

Used together, these two bits specify the various character-available condi-

tions. In Receive Interrupt modes 1, 2, and 3, a Special Receive Condition

can cause an interrupt that modifies the interrupt vector.

Table 16. Vector Results

Result

Ch B

Ch B Transmit Buffer Empty

Ch B External/Status Change

Ch B Receive Character Available

Ch B Special Receive Condition*

Ch A

Ch A Transmit Buffer Empty

Ch A External/Status Change

Ch A Receive Character Available

Ch A Special Receive Condition*

Note: *Special Receive Conditions: Parity Error, Rx Overrun Error, Framing Error, End-

of-Frame (SDLC).

Z80 Datasheet(PDF) 298 Page - Zilog, Inc.