Z80 datasheet(317/330 Pages) ZILOG

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Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

297

Read Register 1

This register contains the Special Receive condition status bits and Residue

codes for the I-Field in the SDLC Receive Mode.

All Sent (D0)

In asynchronous modes, this bit is set when all the characters have

completely cleared the transmitter. Transitions of this bit do not cause inter-

rupts and it is always set in synchronous modes.

Residue Codes 0, 1, and 2 (D3-D1)

In SDLC receive mode, these three bits indicate the length of the I-field,

when the I-field is not an integral multiple of the character length. These

codes are only meaningful for a transfer in which the End-of-Frame bit is

set (SDLC). For a receive character length of eight bits per character, the

codes signify the following:

Table 32. Read Register 1 Special Receive Condition Status

End of

Frame

(SDLC)

CRC/

Framing

Error

Receiver

Overrun

Error

Parity

Error

Residue

Code 2

Residue

Code 1

Residue

Code 0

All sent

Table33. ResidueCodes

Residue Code

I-Field Bits in

Previous Byte

I-Field Bits in

Second

Previous Byte

10003

01004

11005

00106

10107

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