Z80 datasheet(314/330 Pages) ZILOG

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

294

this bit and sets the External/Status interrupt. When the External/Status

interrupt is set by the change in state of any other input or condition, this bit

shows the inverted state of the SYNC pin at the time of the change. This bit

must be read immediately following a Reset External/Status Interrupt

command to read the current state of tile SYNC input.

Figure 122. Read Register 0

In the External Sync mode, the Sync/Hunt bit operates similar to the Asyn-

chronous mode, except the Enter Hunt Mode control bit enables the

external sync detection logic. When the External Sync Mode and Enter

Hunt Mode bits are set for example, when the receiver is enabled following

a reset, the SYNC input must be held High by the external logic until

external character synchronization is achieved. A High at the SYNC input

holds the Sync/Hunt status bit in the reset condition.

When external synchronization is achieved, SYNC must be driven Low on

the second rising edge of RxC after that rising edge of RxC on which the

last bit of the sync character was received. In other words, after the sync

pattern is detected, the external logic must wait for two full Receive Clock

cycles to activate the SYNC input. When SYNC is forced Low, keep it Low

until the CPU informs the external sync logic that synchronization is lost or

that a new message is about to start. Refer to Figure 122 for timing details.

The High-to-Low transition of the SYNC input sets the Sync/Hunt bit,

which, in turn, sets the External/Status interrupt. The CPU must clear the

interrupt by issuing the Reset External/Status Interrupt command.

Rx Character Available

INT Pending (CH.A Only

Tx Buffer Empty

DCD

SYNC/Hunt

Tx Underrun/EOM

Break/Abort

*Used with ‘External/Status Interrupt Mode

CTS

Z80 Datasheet(PDF) 314 Page - Zilog, Inc.