Z80 datasheet(312/330 Pages) ZILOG

312 / 330 page

<%27 2GTKRJGTCNU

7UGT /CPWCN

UM008101-0601

Serial Input/Output

292

Read Registers

The Z80 SIO contains three registers, RR2-RR0 (Figure 122 through

Figure 124), that are read to obtain the status information for each channel,

with the exception of RR2-Channel B. The status information includes error

conditions, interrupt vector, and standard communications-interface signals.

To read the contents of a selected read register other than RRD, the system

program must first write the pointer byte to WR0, in exactly the same way

as a write register operation. Then, by executing an input instruction, the

contents of the addressed read register can be read by the CPU.

The status bits of RR0 and RR1 are carefully grouped to simplify status

monitoring. For example, when the interrupt vector indicates that a Special

Receive Condition interrupt occurred, all the appropriate error bits can be

read from a single register (RR1).

Read Register 0

This register contains the status of the receive and transmit buffers; the

DCD,CTS, and SYNC inputs; the Transmit Underrun/EOM latch; and the

Break/Abort latch.

Receive Character Available (DO)

This bit is set when at least one character is available in the receive buffer;

it is reset when the receive FIFO is empty.

Table 31. Read Register 0 Rx and Tx Buffers

IDS

D4D3

D2D1D0

Break/

Abort

Transmit

Underrun

EOM

CTS

Sync/

Hunt

Buffer

Empty

DCD

Transmit

Pending

Interrupt

Pending

(Ch.A

only)

Receive

Character

available

Z80 Datasheet(PDF) 312 Page - Zilog, Inc.

Z80 Datasheet(HTML) 312 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL