WM8994 datasheet(4/359 Pages) WOLFSON

4 / 359 page

WM8994

Production Data

PD, April 2012, Rev 4.4

ANALOGUE OUTPUTS ............................................................................................... 137

SPEAKER OUTPUT CONFIGURATIONS..................................................................................................................... 137

HEADPHONE OUTPUT CONFIGURATIONS............................................................................................................... 140

EARPIECE DRIVER OUTPUT CONFIGURATIONS..................................................................................................... 141

LINE OUTPUT CONFIGURATIONS.............................................................................................................................. 141

GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 145

GPIO CONTROL ........................................................................................................................................................... 145

GPIO FUNCTION SELECT ........................................................................................................................................... 148

BUTTON DETECT (GPIO INPUT)................................................................................................................................. 149

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) .................................................................................................. 149

SDOUT (4-WIRE SPI CONTROL INTERFACE DATA) ................................................................................................. 150

INTERRUPT (IRQ) STATUS OUTPUT.......................................................................................................................... 150

OVER-TEMPERATURE DETECTION........................................................................................................................... 150

ACCESSORY DETECTION (MICBIAS CURRENT DETECTION) ................................................................................ 151

FREQUENCY LOCKED LOOP (FLL) LOCK STATUS OUTPUT .................................................................................. 152

SAMPLE RATE CONVERTER (SRC) LOCK STATUS OUTPUT ................................................................................. 152

DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION...................................................................... 152

CONTROL WRITE SEQUENCER STATUS DETECTION ............................................................................................ 154

DIGITAL CORE FIFO ERROR STATUS DETECTION.................................................................................................. 154

OPCLK CLOCK OUTPUT.............................................................................................................................................. 155

FLL CLOCK OUTPUT.................................................................................................................................................... 155

INTERRUPTS .............................................................................................................. 156

DIGITAL AUDIO INTERFACE...................................................................................... 162

MASTER AND SLAVE MODE OPERATION................................................................................................................. 163

OPERATION WITH TDM............................................................................................................................................... 163

AUDIO DATA FORMATS (NORMAL MODE)................................................................................................................ 164

AUDIO DATA FORMATS (TDM MODE) ....................................................................................................................... 167

DIGITAL AUDIO INTERFACE CONTROL ................................................................... 169

AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL................................................................................................ 169

AIF1 - SIGNAL PATH ENABLE ..................................................................................................................................... 170

AIF1 - BCLK AND LRCLK CONTROL ........................................................................................................................... 170

AIF1 - DIGITAL AUDIO DATA CONTROL..................................................................................................................... 173

AIF1 - MONO MODE ..................................................................................................................................................... 174

AIF1 - COMPANDING ................................................................................................................................................... 175

AIF1 - LOOPBACK ........................................................................................................................................................ 176

AIF2 - MASTER / SLAVE AND TRI-STATE CONTROL................................................................................................ 177

AIF2 - SIGNAL PATH ENABLE ..................................................................................................................................... 178

AIF2 - BCLK AND LRCLK CONTROL ........................................................................................................................... 178

AIF2 - DIGITAL AUDIO DATA CONTROL..................................................................................................................... 181

AIF2 - MONO MODE ..................................................................................................................................................... 182

AIF2 - COMPANDING ................................................................................................................................................... 183

AIF2 - LOOPBACK ........................................................................................................................................................ 183

AUDIO INTERFACE AIF3 CONFIGURATION .............................................................................................................. 184

DIGITAL PULL-UP AND PULL-DOWN.......................................................................................................................... 186

CLOCKING AND SAMPLE RATES.............................................................................. 187

AIF1CLK ENABLE ......................................................................................................................................................... 188

AIF1 CLOCKING CONFIGURATION ............................................................................................................................ 189

AIF2CLK ENABLE ......................................................................................................................................................... 191

AIF2 CLOCKING CONFIGURATION ............................................................................................................................ 191

MISCELLANEOUS CLOCK CONTROLS ...................................................................................................................... 193

BCLK AND LRCLK CONTROL...................................................................................................................................... 196

CONTROL INTERFACE CLOCKING ............................................................................................................................ 196

FREQUENCY LOCKED LOOP (FLL) ............................................................................................................................ 197

FREE-RUNNING FLL CLOCK....................................................................................................................................... 201

GPIO OUTPUTS FROM FLL ......................................................................................................................................... 203

EXAMPLE FLL CALCULATION..................................................................................................................................... 203

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