PC87382 datasheet(22/72 Pages) NSC

22 / 72 page

3.0 Device Architecture and Configuration (Continued)

www.national.com

Revision1.2

3.2.4

Standard Configuration Registers

Figure 5. Conﬁguration Register Map

SuperI/O Conﬁguration Registers

The PC87382 configuration registers at Indexes 20h and 27h are used for part identification. The other configuration

registers are used for global power management and the selection of pin multiplexing options. For details, see Section 3.7

on page 26.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device. See the functional block descriptions in the following sec-

tions.

Control

The only implemented control register for each logical device is the Activate register at Index 30h. Bit 0 of the Activate reg-

ister controls the activation of the associated functional block. Activation enables access to the functional block’s registers,

and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply on a function-

specific basis (such as clock enable and active pinout signaling). Access to the configuration register of the logical device is

enabled even when the logical device is not activated.

Standard Conﬁguration

The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address

descriptor 0 is a pair of registers at Index 60-61h, holding the first 16-bit base address for the register set of the functional

block. An optional 16-bit second base-address (descriptor 1) at Index 62-63h is used for logical devices with more than one

continuous register set. Interrupt Number (Index 70h) and IRQ Type Select (Index 71h) allocate an IRQ line to the block and

control its type. DMA Channel Select 0 (Index 74h) allocates a DMA channel to the block, where applicable. DMA Channel

Select 1 (Index 75h) allocates a second DMA channel, where applicable.

SuperI/O Control and

Conﬁguration Registers

Logical Device Control and

one per Logical Device

Conﬁguration Registers -

Index

07h

Logical Device Number

20h

SuperI/O ID

21h

SuperI/O Conﬁguration 1

22h

SuperI/O Conﬁguration 2

23h-25h

Reserved

26h

SuperI/O Conﬁguration 6

27h

SuperI/O Revision ID

28h

Reserved

29h

Clock Generator Control

2Ah - 2Fh

Reserved exclusively for National use

30h

Logical Device Control (Activate)

60h

I/O Base Address Descriptor 0 Bits 15-8

61h

I/O Base Address Descriptor 0 Bits 7-0

70h

Interrupt Number and Wake-Up on IRQ Enable

71h

IRQ Type Select

74h

DMA Channel Select 0

75h

DMA Channel Select 1

F0h - FFh

Device Speciﬁc Logical Device Conﬁguration 1 to 15

(some are optional)

PC87382 Datasheet(PDF) 22 Page - National Semiconductor (TI)

PC87382 Datasheet(HTML) 22 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL