PC87382 datasheet(25/72 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.4

INTERNAL ADDRESS DECODING

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed register

within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The remaining bits are matched with the base

address register to decode the entire I/O range allocated to the logical device. Therefore the lower bits of the base address

register are forced to 0 (read only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size

of the I/O range.

The base addresses of the Serial Port 1 and FIR modules are limited to the I/O address range of 00h to 7FXh only (bits 11-

15 are forced to 0). The addresses of the non-legacy logical devices are configurable within the full 16-bit address range (up

to FFFXh).

3.5

PROTECTION

The PC87382 provides features to protect the hardware configuration from changes made by application software running

on the host.

The protection is activated by the software setting a “sticky” lock bit. Each lock bit protects a group of configuration bits lo-

cated either in the same register or in different registers. When the lock bit is set, the lock bit and all the protected bits be-

come read only and cannot be further modified by the host through the LPC bus. All the lock bits are reset by Hardware

reset, thus unlocking the protected configuration bits.

The bit locking protection mechanism is optional.

The protected groups of configuration bits are described below.

3.5.1

Configuration Lock

Lock bit:

LOCKMCF in SIOCF1 register (Device Configuration).

Protected bits: LOCKMCF and IOWAIT (in SIOCF1 register) and all bits in SIOCF2 register (Device Configuration).

3.5.2

GPIO Ports Configuration Lock

Protects the configuration (but not the data) of all the GPIO Ports.

Lock bit:

LOCKGCF in SIOCF1 register (Device Configuration).

Protected bits for each GPIO Port: LOCKGCF in SIOCF1 register, and all bits in GPCFG register (except LOCKCFP bit) and

GPEVR register (Device Configuration).

3.5.3

Fast Disable Configuration Lock

Protects the Fast Disable bits for all the Legacy modules.

Lock bit:

LOCKFDS in SIOCF6 register (Device Configuration).

Protected bits: All bits in SIOCF6 register (except General-Purpose Scratch bits) and GLOBEN bit in SIOCF1 register

(Device Configuration).

3.5.4

Clock Control Lock

Protects the Clock Generator control bits.

Lock bit:

LOCKCCF in CLOCKCF register (Device Configuration).

Protected bits: All bits in CLOCKCF register (Device Configuration).

3.5.5

GPIO Ports Lock

Protects the configuration and data of all the GPIO Ports.

Lock bit:

LOCKCFP in GPCFG register, for each GPIO Port (Device Configuration).

Protected bits for each GPIO Port: PUPCTL, OUTTYPE and OUTENA in GPCFG register; the corresponding bit (to the

port pin) in GPDO register (GPIO Ports).

PC87382 Datasheet(PDF) 25 Page - National Semiconductor (TI)

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