PC87382 datasheet(5/72 Pages) NSC

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Table of Contents (Continued)

Revision 1.2

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3.3.2

Floating Module Output ............................................................................................... 24

3.4

INTERNAL ADDRESS DECODING .......................................................................................... 25

3.5

PROTECTION ........................................................................................................................... 25

3.5.1

Configuration Lock ....................................................................................................... 25

3.5.2

GPIO Ports Configuration Lock ................................................................................... 25

3.5.3

Fast Disable Configuration Lock .................................................................................. 25

3.5.4

Clock Control Lock ...................................................................................................... 25

3.5.5

GPIO Ports Lock .......................................................................................................... 25

3.6

3.7

SUPERI/O CONFIGURATION REGISTERS ............................................................................. 26

3.7.1

SuperI/O ID Register (SID) .......................................................................................... 26

3.7.2

SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 27

3.7.3

SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 27

3.7.4

SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 28

3.7.5

SuperI/O Revision ID Register (SRID) ........................................................................ 28

3.7.6

Clock Generator Control Register (CLOCKCF) ........................................................... 29

3.8

INFRARED CONFIGURATION ................................................................................................. 30

3.8.1

Logical Device 2 (IR) Configuration ............................................................................. 30

3.8.2

Infrared Configuration Register ................................................................................... 30

3.9

SERIAL PORT 1 CONFIGURATION ......................................................................................... 31

3.9.1

Logical Device 3 (SP1) Configuration .......................................................................... 31

3.9.2

Serial Port 1 Configuration Register ............................................................................ 31

3.10

GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 32

3.10.1

General Description ..................................................................................................... 32

3.10.2

Implementation ............................................................................................................32

3.10.3

Logical Device 7 (GPIO) Configuration ....................................................................... 33

3.10.4

GPIO Pin Select Register (GPSEL) ............................................................................. 34

3.10.5

GPIO Pin Configuration Register (GPCFG) ................................................................ 34

3.10.6

GPIO Event Routing Register (GPEVR) ...................................................................... 35

3.11

DOCKING LPC SWITCH CONFIGURATION ............................................................................ 36

3.11.1

Logical Device 19 (DLPC) Configuration ..................................................................... 36

4.0

LPC Bus Interface

4.1

OVERVIEW ............................................................................................................................... 37

4.2

LPC TRANSACTIONS ............................................................................................................... 37

4.3

CLKRUN FUNCTIONALITY ...................................................................................................... 37

4.4

INTERRUPT SERIALIZER ........................................................................................................ 37

5.0

General-Purpose Input/Output (GPIO) Port

5.1

OVERVIEW ............................................................................................................................... 38

5.2

BASIC FUNCTIONALITY ..........................................................................................................39

5.2.1

Configuration Options .................................................................................................. 39

5.2.2

Operation ..................................................................................................................... 39

PC87382 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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