PC87382 datasheet(65/72 Pages) NSC

65 / 72 page

8.0 Device Characteristics (Continued)

Revision 1.2

www.national.com

8.4.4

LCLK and LRESET

Symbol

Parameter

Min

Max

Units

tCYC

1. The PCI may have any clock frequency between nominal DC and 33 MHz.

Device operational parameters at frequencies under 16 MHz can be guaranteed

by design rather than by testing. The clock frequency can be changed at any

time during the operation of the system as long as the clock edges remain

“clean” (monotonic) and the minimum cycle and high and low times are not vio-

lated. The clock may only be stopped in a low state.

LCLK Cycle Time

tHIGH

LCLK High Time2

2. Not tested. Guaranteed by characterization.

tLOW

LCLK Low Time2

LCLK Slew Rate3,4

3. Not tested. Guaranteed by design

4. Rise and fall times are speciﬁed in terms of the edge rate measured in V/ns.

This slew rate must be met across the minimum peak-to-peak portion of the

clock wavering as shown below.

V/ns

LRESET Slew Rate3,5

5. The minimum LRESET slew rate applies only to the rising (de-assertion) edge of

the reset signal, and ensures that system noise cannot render an otherwise

monotonic signal to appear to bounce in the switching range.

mV/ns

tWRST

LRESET pulse width

100

0.6 VDD

0.2 VDD

0.5 VDD

0.4 VDD

0.3 VDD

0.4 VDD p-to-p

(minimum)

tHIGH

tLOW

3.3V Clock

tCYC

PC87382 Datasheet(PDF) 65 Page - National Semiconductor (TI)

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