PC87382 datasheet(4/72 Pages) NSC

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Revision 1.2

Table of Contents

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAM ...........................................................................................................8

1.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 9

1.3

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 10

1.3.1

LPC Bus Interface ....................................................................................................... 10

1.3.2

Docking LPC Bus ........................................................................................................ 10

1.3.3

Clocks .......................................................................................................................... 10

1.3.4

Infrared (IR) ................................................................................................................ 11

1.3.5

Serial Port (SP1) ..........................................................................................................11

1.3.6

General-Purpose Input/Output (GPIO) Ports ............................................................... 11

1.3.7

Power and Ground ..................................................................................................... 12

1.3.8

Strap Configuration ...................................................................................................... 12

1.3.9

Test and Miscellaneous ............................................................................................... 12

1.4

INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 13

2.0

Power, Reset and Clocks

2.1

POWER ..................................................................................................................................... 14

2.1.1

Power Planes .............................................................................................................. 14

2.1.2

Power States ...............................................................................................................14

2.1.3

Power Connection and Layout Guidelines .................................................................. 14

2.2

RESET SOURCES AND TYPES ............................................................................................... 15

2.2.1

VDD Power-Up Reset .................................................................................................. 15

2.2.2

Hardware Reset ........................................................................................................... 15

2.3

CLOCK DOMAINS ..................................................................................................................... 15

2.3.1

LPC Domain ................................................................................................................ 15

2.3.2

48 MHz Domain ........................................................................................................... 15

2.3.3

Chip Power-Up ............................................................................................................ 16

2.3.4

Specifications .............................................................................................................. 16

2.4

TESTABILITY SUPPORT ..........................................................................................................16

2.4.1

ICT ............................................................................................................................... 16

2.4.2

XOR Tree Testing ........................................................................................................ 16

2.4.3

Test Mode Entry Sequence ......................................................................................... 17

3.0

Device Architecture and Configuration

3.1

OVERVIEW ............................................................................................................................... 18

3.2

CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 18

3.2.1

The Index-Data Register Pair ...................................................................................... 18

3.2.2

Banked Logical Device Registers Structure ................................................................ 19

3.2.3

Standard Configuration Register Definitions ............................................................... 20

3.2.4

Standard Configuration Registers ............................................................................... 22

3.2.5

Default Configuration Setup ........................................................................................ 23

3.3

MODULE CONTROL ................................................................................................................. 24

3.3.1

Module Enable/Disable ................................................................................................ 24

PC87382 Datasheet(PDF) 4 Page - National Semiconductor (TI)

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