PC87382 datasheet(42/72 Pages) NSC

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5.0 General-Purpose Input/Output (GPIO) Port (Continued)

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Revision1.2

5.4.1

GPIO Pin Configuration Registers Structure

For each GPIO Port, there is a group of eight identical sets of configuration registers. Each set is associated with one GPIO

pin. The entire group is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register (see

Section 3.10.4 on page 34), which functions as an index register for the pin, and the selected GPCFG and GPEVR registers,

which reflect the configuration of the currently selected pin (see Table 20).

5.4.2

GPIO Port Runtime Register Map

5.4.3

GPIO Data Out Register (GPDO)

Location: Device specific

Type:

R/W

Table 20. GPIO Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Reset

F0h

GPIO Pin Select register (GPSEL)

R/W

00h

F1h

GPIO Pin Conﬁguration register 1 (GPCFG)

Varies per bit 04h or 44h1

1. Depending on port number

F2h

GPIO Pin Event Routing register (GPEVR)

R/W or RO

01h

Offset

Mnemonic

Type

Section

Device speciﬁc 1

1. The location of this register is deﬁned in Section 3.10.3 on page 33.

GPDO

GPIO Data Out

R/W

5.4.3

Device speciﬁc 1

GPDI

GPIO Data In

5.4.4

Device speciﬁc 1

GPEVEN

GPIO Event Enable

R/W

5.4.5

Device speciﬁc 1

GPEVST

GPIO Event Status

R/W1C

5.4.6

Bit

76543210

Name

DATAOUT

Reset

11111111

Bit

Description

7-0

DATAOUT (Data Out). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. The value of each bit determines the

value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the

written data, unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless

of the pin value and conﬁguration.

0: Corresponding pin driven to low.

1: Corresponding pin driven or released (according to buffer type selection) to high (default).

PC87382 Datasheet(PDF) 42 Page - National Semiconductor (TI)

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