PC87382 datasheet(43/72 Pages) NSC

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5.0 General-Purpose Input/Output (GPIO) Port (Continued)

Revision 1.2

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5.4.4

GPIO Data In Register (GPDI)

Location: Device specific

Type:

5.4.5

GPIO Event Enable Register (GPEVEN)

Location: Device specific

Type:

R/W

5.4.6

GPIO Event Status Register (GPEVST)

Location: Device specific

Type:

R/W1C

Bit

76543210

Name

DATAIN

Reset

XXXXXXXX

Bit

Description

7-0

DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. Reading each bit returns the value of the

corresponding GPIO pin. Pin conﬁguration and the GPDO register value may inﬂuence the pin value. Writes are

ignored.

0: Corresponding pin level low.

1: Corresponding pin level high.

Bit

76543210

Name

EVTENA

Reset

00000000

Bit

Description

7-0

EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. Each bit enables system

notiﬁcation by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in GPEVST

0: Event pending by corresponding GPIO pin masked.

1: Event pending by corresponding GPIO pin enabled.

Bit

76543210

Name

EVTSTAT

Reset

00000000

Bit

Description

−0 EVTSTAT (Event Status). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. The setting of each bit is

independent of the Event Enable bit in GPEVEN register. An active event sets the Status bit, which may be

cleared only by software writing 1 to the bit.

0: No active edge or level detected since last cleared.

1: Active edge or level detected.

PC87382 Datasheet(PDF) 43 Page - National Semiconductor (TI)

PC87382 Datasheet(HTML) 43 Page - National Semiconductor (TI)

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