PC87382 datasheet(24/72 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.3

MODULE CONTROL

3.3.1

Module Enable/Disable

Module control is performed primarily through the Activation bit (bit 0 of Index 30h) of each logical device. The operation of

each module can be controlled by the host through the LPC bus.

Module enable/disable by the host through the LPC bus is controlled by the following bits:

Activation bit (bit 0) in Index 30h of the Standard conﬁguration registers; see Section 3.2.3 on page 20.

Fast Disable bit in SIOCF6 register; for the Serial Port 1 and IR modules only; see Section 3.7.4 on page 28.

Global Enable bit (GLOBEN) in SIOCF1 register; see Section 3.7.2 on page 27.

A module is enabled only if all of these bits are set to their “enable” value.

When a legacy (SP1 or IR) module is disabled, the following takes place:

The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned.

Access to the standard- and device-specific Logical Device configuration registers through the LPC bus remains enabled.

Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is

not generated).

The module’s internal clock is disabled (the module is not functional) to lower the power consumption.

When the GPIO or DLPC module is disabled, the following takes place:

The host system resources of the logical device (IRQ and runtime address range) are unassigned.

Access to the standard- and device-specific Logical Device configuration registers through the LPC bus remains enabled.

Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is

not generated).

The module is functional.

3.3.2

Floating Module Output

The pins of the Legacy modules (Serial Port, Infrared) can be floated. When the TRI-STATE Control bit (bit 0) is set in the

specific module configuration register (at Index F0h of the specific logical device in the configuration space) and the module

is disabled (see Section 3.3.1), the module output signals are floated and the I/O signals are configured as inputs (note that

the logic level at the inputs is ignored by the module, which is disabled).

Figure 6 shows the control mechanism for floating the pins of a Legacy module.

Figure 6. Control of Floating Legacy Module Pins

Fast

Disable

xxxDIS1

SIOCF6

TRI-

STATE

Control

Conﬁguration

Global

Enable

GLOBEN

SIOCF1

Activation

Bit (bit 0)

Index 30h

Device Conﬁguration

Legacy Module

Module

Module Enable

(Index F0h)

Legacy

Enable

Output

Buffer

1. Wherever the bit is implemented

PC87382 Datasheet(PDF) 24 Page - National Semiconductor (TI)

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