PC87382 datasheet(34/72 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.10.4 GPIO Pin Select Register (GPSEL)

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the

GPIO Pin Configuration register). It is reset by hardware to 00h.

Location: Index F0h

Type:

R/W

3.10.5 GPIO Pin Configuration Register (GPCFG)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register (GPSEL). All

the GPIO Pin registers that are accessed via this register have a common bit structure, as shown below. This register is

reset by hardware to 44h for port 0, and to 04h for port 2.

Location: Index F1h

Type:

Varies per bit

Port 0, bits 0-4 (with event detection capability)

Port 2, bits 0,1,3 (without event detection capability)

Bit

76543210

Name

Reserved

PORTSEL

Reserved

PINSEL

Reset

00000000

Bit

Description

7-6

Reserved.

5-4

PORTSEL (Port Select). These bits select the GPIO port to be configured:

Bits

5 4

GPIO Port

0 0:

Port 0 (default)

0 1:

Reserved

1 0:

Port 2

1 1:

Reserved

Reserved.

2-0

PINSEL (Pin Select). These bits select the GPIO pin to be conﬁgured in the selected port:

000, 001,... 111: Binary value of the pin number, 0, 1,... 7 respectively (default=0).

For port 2 only values 000,001,011 are legal.

Bit

76543210

Name

Reserved

EVDBNC

EVPOL

EVTYPE

LOCKCFP

PUPCTL

OUTTYPE

OUTENA

Reset

01000100

Bit

76543210

Name

Reserved

LOCKCFP

PUPCTL

OUTTYPE

OUTENA

Reset

00000100

Bit

Type

Description

Reserved.

R/W or

EVDBNC (Event Debounce Enable). (Ports 0 and 1 with event detection capability). Enables

transferring the signal only after a predetermined debounce period.

0: Disabled.

1: Enabled (default).

Reserved. (Port 2). Always 0.

PC87382 Datasheet(PDF) 34 Page - National Semiconductor (TI)

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