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PC87382 Datasheet(PDF) 71 Page - National Semiconductor (TI) |
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PC87382 Datasheet(HTML) 71 Page - National Semiconductor (TI) |
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71 / 72 page  8.0 Device Characteristics (Continued) Revision 1.2 71 www.national.com 8.4.10 Docking LPC Switch Timing Symbol Parameter Min Max Unit tON Switch On after RE LCLK1 1. Not tested. Guaranteed by characterization. 014 ns tOFF Switch Off after RE LCLK1 028 ns tSW Delay from Switch Enable Command to Switch On2,3 2. Not tested. Guaranteed by design. 3. The time is measured from the end of the corresponding LPC transaction. 4*tCYC 4 4. tCYC is LCLK cycle time. - tCLK2RST Delay from Switch Enable Command to DLRESET de-assertion and DLFRAME, DLAD connection2 CLK2RSTVAL5 5. Defined by CLK2RSTVAL field of the DLCTL register; see Section 6.3.2 on page 45. - tSU DLDRQ setup time before RE LCLK 7 ns tH DLDRQ hold time after RE LCLK 0 ns tSWPD Switch Propagation Delay1 300 ps Connected Held by Pull-ups Connected tON tSW tOFF tON tSW Switch On/Off Command LCLK DLCLK, DCLKOUT, DLFRAME, DLAD DLRESET Held by Pull-ups tCLK2RST DSERIRQ Held by Pull-down Driven DCLKRUN, |
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