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5.0 General-Purpose Input/Output (GPIO) Port (Continued)

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Figure 11. GPIO Event Routing Mechanism

The GPEVST register reflects the event source pending status.

Active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for falling

edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level). The

corresponding bit of the GPEVST register is set by hardware whenever an active edge is detected, regardless of any other

bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.

A GPIO pin is in event pending state if the corresponding bit of the GPEVEN register is set and one of the following is true:

The Event Type is level and the pin is at active level.

The Event Type is edge and the corresponding bit of the GPEVST register is set.

The target means of system notification is asserted if at least one GPIO pin is in event pending state.

The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the

means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configura-

tion. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated.

System event notification functionality is provided even when the GPIO pin is enabled as output.

A pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source must not

be released by software (except for disabling the source) as long as the pin is at active level. When a level event is used, it

is recommended to disable the input debouncer.

On de-activation of the GPIO port, the GPEVST register is cleared, and access to both the GPEVST and GPEVEN registers

is disabled. The target IRQ line is detached from the GPIO and de-asserted.

Before enabling any system notification, it is recommended to first set the desired event configuration and then verify that

the status registers are cleared.

5.4

GPIO PORT REGISTERS

The register maps in this chapter use the following abbreviations for Type:

R/W

= Read/Write.

= Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a

different register.

= Write.

= Read Only.

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

GPIO Event Pending Indication

IRQ

Event

Routing

Logic

Enable

IRQ

Event Routing Register

Bit 0

(GPEVR)

Routed Events

from other GPIO Pins

Routing

GPIO Pin

GPIO Event to

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