PC87382 datasheet(45/72 Pages) NSC

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6.0 Docking LPC Switch (Continued)

Revision 1.2

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6.3

DOCKING LPC SWITCH REGISTERS

The register maps in this chapter use the following abbreviations for Type:

R/W = Read/Write.

RO = Read Only.

6.3.1

Docking LPC Switch Register Map

6.3.2

Docking LPC Control (DLCTL)

This register is reset by VDD Power-Up reset.

Location: Device specific

Type:

R/W

Offset

Mnemonic

Type

Section

Device speciﬁc 1

1. The location of this register is deﬁned in the Section 3.11.1 on page 36.

DLCTL

Docking LPC Control

R/W

6.3.2

Device speciﬁc 1

Reserved

Bit

76543210

Name

Reserved

EXP

CLK2RSTVAL

DLCON

Reset

00000000

Bit

Type

Description

7-4

Reserved.

3RO

EXP (Timer Expired). When set, this bit indicates that the CLK2RST timer expired. The bit is

cleared on the switch disconnection.

2-1

R/W

CLK2RSTVAL (CLK2RST Timer Value). Deﬁnes the minimum time interval from the connection of

DLCLK until DLRESET de-assertion. The interval is measured in LCLK clock cycles.

Bits

2 1

Minimum Time Interval

0 0:

0 - the Timer is disabled (default)

0 1:

33*tCYC

1 0:

330*tCYC

1 1:

3300*tCYC

R/W

DLCON (Docking LPC Connect). Setting this bit triggers the Docking LPC Connection procedure.

Clearing this bit disables the switch.

PC87382 Datasheet(PDF) 45 Page - National Semiconductor (TI)

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