CL-PD6722 datasheet(79/128 Pages) CIRRUS

79 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

USING GPSTB PINS FOR EXTERNAL PORT CONTROL

(CL-PD6722 only)

12.2 Example Implementations of GPSTB-Controlled Read and Write Ports

Figure 12-1. Example GPSTB Write Port (Extension Control 2 bits 4:3 are ‘10’)

In this mode, Extension Control 2 register bit 4 is set to ‘1’ enabling the GPSTB pin to function as a write

strobe. Writes to the respective extended index 0Ah cause the respective GPSTB to go active (low) for

the duration of the system’s IOW* pulse.

On writes, data is written to both the external latch and the internal shadow copy of the External Data

Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes all ‘0’s

at its outputs when the CL-PD67XX is reset.

Figure 12-2. Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘01’)

In this mode, Extension Control 2 register bit 3 is set to ‘1’, enabling the respective GPSTB pin to function

as a read strobe. Reads from the corresponding extended index 0Ah cause GPSTB to go active (default

active level is low) for the duration of the system’s IOR* pulse.

NOTE: Data is still written to the shadowed External Data register on writes to Extended Index 0Ah but is not

visible.

IOW*

SD[15:0]

GPSTB

Latch

RES

EXT_WR*

SD[15:8]

(16-bit bus)

General-

Purpose

Outputs

PWRGOOD

Pull-up†

† Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.

(for example, ’374)

CL-PD6722

IOR*

SD[15:0]

GPSTB

Tristate Buffer

EXT_RD*

SD[15:8]

(16-bit bus)

General-

Purpose

Inputs

† Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.

Pull-up†

(for example, ’244)

CL-PD6722

CL-PD6722 Datasheet(PDF) 79 Page - Cirrus Logic

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