CL-PD6722 datasheet(97/128 Pages) CIRRUS

97 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

ELECTRICAL SPECIFICATIONS

15.3.5

Input Clock Speciﬁcation

Figure 15-5. Input Clock Speciﬁcation

Table 15-11.Input Clock Speciﬁcation

Symbol

Parameter

MIN

MAX

Units

Conditions

CLK pin input rise time

CLK pin input fall time

CLK input low period

0.4 TCLKP

0.6 TCLKP

CLK input high period

0.4 TCLKP

0.6 TCLKP

Vcenter

Center voltage at which

period speciﬁed

0.5 VDD

TCLKP

Input clock period,

internal clock

69.84 – 0.1%

69.84 + 0.1%

Normal synthesizer

operation. Misc Control

2 register, bit 0 = ‘0’.

CLK pin at 14.318 MHz.

TCLKP

Input clock period,

external clock

40 – 0.1%

40 + 0.1%

Synthesizer bypassed.

Misc Control 2 register,

bit 0 = ‘1’.

CLK pin at 25 MHz.

VIHmin

CLK input high voltage

2.0

CORE_VDD = 3.0 V

VILmax

CLK input low voltage

0.8

CORE_VDD = 3.6 V

VIHCmin

CLK input high voltage

0.7 VDD

CORE_VDD = 4.5 V

VILCmax

CLK input low voltage

0.2 VDD

CORE_VDD = 5.5 V

VILmax, VILCmax

TCLKP

CLK

VIHmin, VIHCmin

Vcenter

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