CL-PD6722 datasheet(35/128 Pages) CIRRUS

35 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

OPERATION REGISTERS

a Socket B is available on the dual-socket CL-PD6722.

b This register affects both sockets (it is not speciﬁc to either socket).

c These registers are not available on the CL-PD6710.

ATA Control

26h

66h

Chapter 9:

Extension

Scratchpad

27h

67h

–

System Memory Map 3 Start Address Low

28h

68h

Chapter 8:

Memory Window

Mapping

System Memory Map 3 Start Address High

29h

69h

System Memory Map 3 End Address Low

2Ah

6Ah

System Memory Map 3 End Address High

2Bh

6Bh

Card Memory Map 3 Offset Address Low

2Ch

6Ch

Card Memory Map 3 Offset Address High

2Dh

6Dh

Extended Index:c

Scratchpad

Data Mask 0

Data Mask 1

Extension Control 1 (formerly DMA

Control)

Maximum DMA Acknowledge Delay

Reserved

External Data

Extension Control 2

2Eh

6Eh

Chapter 9:

Extension

Extended index 00h

Extended index 01h

Extended index 02h

Extended index 03h

Extended index 04h

Extended index 05h–09h

Extended index 0Ah

Extended index 0Bh

–

Extended Data

2Fh

6Fh

System Memory Map 4 Start Address Low

30h

70h

Chapter 8:

Memory Window

Mapping

System Memory Map 4 Start Address High

31h

71h

System Memory Map 4 End Address Low

32h

72h

System Memory Map 4 End Address High

33h

73h

Card Memory Map 4 Offset Address Low

34h

74h

Card Memory Map 4 Offset Address High

35h

75h

Card I/O Map 0 Offset Address Low

36h

76h

Chapter 7:

I/O Window

Mapping

Card I/O Map 0 Offset Address High

37h

77h

Card I/O Map 1 Offset Address Low

38h

78h

Card I/O Map 1 Offset Address High

39h

79h

Setup Timing 0

3Ah

7Ah

Chapter 10:

Timing

Command Timing 0

3Bh

7Bh

Recovery Timing 0

3Ch

7Ch

Setup Timing 1

3Dh

7Dh

Command Timing 1

3Eh

7Eh

Recovery Timing 1

3Fh

7Fh

Table 5-1.

Index Registers (cont.)

Index Value

Chapter

Page

Number

Socket A

Socket Ba

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