CL-PD6722 datasheet(45/128 Pages) CIRRUS

45 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

CHIP CONTROL REGISTERS

6.6

Management Interrupt Conﬁguration

This register controls which status changes may cause management interrupts and at which pin the man-

agement interrupts will appear.

Bit 0 — Battery Dead Or Status Change Enable

When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s

Battery Dead Or Status Change bit (see page 44) is ‘1’. This allows management interrupts to be

generated on changes in level of the BVD1/-STSCHG pin.

Bit 1 — Battery Warning Enable

When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s

Battery Warning Change bit (see page 44) is ‘1’. This bit is ignored when the card socket is in I/O

mode.

Bit 2 — Ready Enable

When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s

Ready Change bit (see page 44) is ‘1’.

Bit 3 — Card Detect Enable

When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s

Card Detect Change bit (see page 44) is ‘1’.

Index: 05h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Management IRQ Select

Card Detect

Enable

Ready Enable

Battery

Warning

Enable

Battery Dead

Or Status

Change

Enable

RW:0000

RW:0

Battery Dead Or Status Change management interrupt disabled.

If Battery Dead Or Status Change is ‘1’, a management interrupt will occur.

Battery Warning Change management interrupt disabled.

If Battery Warning Change is ‘1’, a management interrupt will occur.

Ready Change management interrupt disabled.

If Ready Change is ‘1’, a management interrupt will occur.

Card Detect Change management interrupt disabled.

If Card Detect Change is ‘1’, a management interrupt will occur.

CL-PD6722 Datasheet(PDF) 45 Page - Cirrus Logic

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