CL-PD6722 datasheet(52/128 Pages) CIRRUS

52 / 128 page

PRELIMINARY DATA SHEET v3.1

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

I/O WINDOW MAPPING REGISTERS

7.6

Card I/O Map 0–1 Offset Address Low

There are two separate Card I/O Map Offset Address Low registers, each with identical ﬁelds. These reg-

isters are located at the following indexes:

Index

Card I/O Map Offset Address Low

36h

Card I/O Map 0 Offset Address Low

38h

Card I/O Map 1 Offset Address Low

Bits 7:1 — Offset Address 7:1

This register contains the least-signiﬁcant byte of the quantity that will be added to the host I/O

address; this will determine the PC Card I/O map location where the I/O access will occur.

The most-signiﬁcant byte is located in the Card I/O Map 0–1 Offset Address High register (see

page 52).

7.7

Card I/O Map 0–1 Offset Address High

There are two separate Card I/O Map Offset Address High registers, each with identical ﬁelds. These reg-

isters are located at the following indexes:

Index

Card I/O Map Offset Address High

37h

Card I/O Map 0 Offset Address High

39h

Card I/O Map 1 Offset Address High

Bits 15:8 — Offset Address 15:8

This register contains the most-signiﬁcant byte of the Offset Address. See the description of the

End Address ﬁeld associated with bits 7:1 of the Card I/O Map 0–1 Offset Address Low register

(see page 52).

a This bit must be programmed to ‘0’.

Index: 36h, 38h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Offset Address 7:1

0 a

RW:0000000

RW:0

Index: 37h, 39h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Offset Address 15:8

RW:00000000

CL-PD6722 Datasheet(PDF) 52 Page - Cirrus Logic

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