CL-PD6722 datasheet(29/128 Pages) CIRRUS

29 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

INTRODUCTION

3.1.10

Write FIFO

To increase performance when writing to PC Cards,

two, independent, four-word-deep write FIFOs are

used. Writes to PC Cards will complete without wait

states until the FIFO is full. Register states should

not be changed until the write FIFO is empty.

3.1.11

Bus Sizing

The CL-PD67XX incorporates logic to automatically

detect its connection to 8- or 16-bit buses. This is

accomplished by sensing SBHE* input activity. If the

SBHE* pin is always high (that is, tied to ISA_VCC),

the CL-PD67XX operates in 8-bit mode where all

transfers occur on the lower data bus, bits 7:0. Any

occurrence of the SBHE* going low triggers the

CL-PD67XX to operate thereafter as a 16-bit device.

16-bit operation of the CL-PD67XX is properly trig-

gered when the SBHE* input is connected to the

system’s SBHE* signal. When the CL-PD67XX is

operating in 16-bit mode, all ISA bus transactions

are 16-bit whenever possible, even if installed PC

cards only support 8-bit transfers. In 16-bit mode,

the signals SBHE* and SA0 are used to specify the

width of the data transfer and the location of data on

the bus (which byte lane has the data) during 8-bit

transfers. The possible combinations for SBHE* and

SA0 are shown in Table 3-2 and Table 3-3.

a The SBHE* signal is pulled up. If the SBHE*

signal remains high, the CL-PD67XX causes

all transfers to occur on D[7:0] only.

Typically, there are three types of data transfers to

and from the CL-PD67XX:

16-Bit Transfer from 16-Bit Processor — The

CPU puts the address on the bus. Then the

CL-PD67XX identiﬁes the address on the bus as

either an 8- or 16-bit transfer. If the transfer is

identiﬁed as 16-bit, the host acknowledges with

the appropriate signal, either MEMCS16* or

IOCS16*. Data is transferred to/from the data

bus as a word on both byte lanes.

8-Bit Transfer from 16-Bit Processor — The

CPU puts the address on the bus. Then the

CL-PD67XX identiﬁes the address on the bus as

either an 8- or 16-bit transfer. In this case, the

transfer is identiﬁed as an 8-bit transfer. The host

queries SA0 and SBHE* to determine the byte

lane on which the transfer is to occur. The data is

transferred to/from the data bus (see Table 3-2).

8-Bit Transfer from 8-Bit Processor — The

CPU puts the address on the bus. The host

determines that it will be an 8-bit transfer since

the SBHE* signal has been tied high. The

CL-PD67XX queries SA0 to determine if the byte

is odd/even. The data is transferred to/from the

Data bus (D[7:0]).

3.1.12

Programmable PC Card Timing

The Setup, Command, and Recovery time for the

PC Card bus is programmable (see Chapter 10).

The CL-PD67XX can be programmed to match the

timing requirements of any PC Card. There are two

sets of timing registers, Timer Set 0 and Timer Set 1,

that can be selected on a per-window basis for both

I/O and memory windows.

To be compatible with the 82365SL, the two timing

sets are programmed at the r ising edge of

PWRGOOD to include normal-wait and one-wait-

state timing.

3.1.13

ATA Mode Operation

The CL-PD67XX supports direct connection to

AT-attached-interface hard drives. ATA drives use

an interface very similar to the IDE interface found

on many popular portable computers. In this mode,

the address and data conﬂict with the ﬂoppy drive is

handled automatically. See Chapter 11 for more

information.

Table 3-2.

16-Bit Mode Operation

16-Bit Mode Transfer Types

SBHE*

SA0

Word

Upper Byte/Odd Address

Low Byte/Even Address

Not Valid

Table 3-3.

8-Bit Mode Operation

8-Bit Mode Transfer Typesa

SA0

Even Address

Odd Address

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