PC87427 datasheet(27/46 Pages) NSC

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2.0 Device Characteristics (Continued)

Revision 1.0

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2.5.2

Reset Timing

VSB Power-Up Reset

Figure 4. Internal VSB Power-Up Reset - Ended by 32 KHz Clock Domain

Symbol

Figure

Description

Reference Conditions

Min1

1. Not tested. Guaranteed by design.

Max1

tLRST

Minimum LRESET active

time

VSB power-up to end of LRESET

10 ms

tIRST

Internal Power-Up Reset

Time

VSB power-up to

end of internal reset

Ended by

32 KHz

Clock Domain

17 * t32KOSC

t32KW +

t32KVAL

2 +

17 * t32KOSC

2. t32KW +t32KVAL from VBAT power-up to 32 KHz domain toggling if VSB and VBAT are powered-up together; see

“Low Frequency Clock Timing” on page 31.

Ended by

LRESET

tLRST

tEPLV

External strap pull-down

resistors, valid time

Before end of internal reset

tIRST

tIPLV

Internal strap pull-up

resistors, valid time3

3. Active only during VSB Power-Up reset.

Before end of internal reset

tIRST

VSB (Power)

(Internal)

tIRST

VSBONmin

t32KOSC

t32KW + t32KVAL

LRESET

VSB Power-Up Reset

(Internal)

32 KHz Domain

Internal Straps

tIPLV

tEPLV

(Pull-Up)

(Pull-Down)

External Straps

PC87427 Datasheet(PDF) 27 Page - National Semiconductor (TI)

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