PC87427 datasheet(2/46 Pages) NSC

2 / 46 page

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Revision 1.0

Features

System Health Support

SensorPath interface to sensors optimizes digital/ana-

log partitioning

— Simpliﬁes board design and routing

— Supports distributed sensors and centralized control

— Off-loads SMBus, faster boot time

Fan Monitor and Control (FMC)

— Four PWM-based fan controls

— Eight 16-bit resolution tachometer inputs

— Software or local temperature feedback control

Chassis intrusion detection

Bus Interfaces

LPC Bus Interface

— Based on Intel’s LPC Interface Speciﬁcation Revi-

sion 1.0, September 29, 1997

— Synchronous cycles using up to 33 MHz bus clock

— 8-bit I/O and 8-bit Memory read and write cycles

— Up to four 8-bit DMA channels

— Serial IRQ

— Supports bootable memory

— Supports LPC and FWH boot transactions

— Supports registers memory and I/O mapping

SMBus Interface

— Compliant with SMBus Speciﬁcation Revision 2.0,

August 3, 2000

— Enables a system controller to access the internal

functions and the fast X-Bus extension

— Proprietary commands for read/write byte from/to:

❏

Internal register

❏

X-Bus I/O device

❏

X-Bus memory device

— Slave address:

❏

One of two values selected by strap

❏

Programmable through the LPC bus

❏

VBAT backed-up

— Supports SMBALERT

— Concurrent access with the LPC bus

— VSB powered

— Optional internal pull-up on the two SMBus pins

Fast X-Bus Extension

— Supports I/O and memory read/write operations

— 8- or 16-bit data bus, 28-bit addressing

— Accessible from both LPC bus and SMBus

— VSB powered

— Boot conﬁguration selected by straps

— Programmable protection control for access from the

LPC bus

— Supports three XIRQ external interrupts

— Multiplexed address-data lines:

❏

Four direct address lines

❏

Partial non-multiplexed option

— Four chip-select outputs, each supporting multiple

zones:

❏

Two BIOS memory zones (up to 32 Mbytes total)

❏

Two user-deﬁned memory zones

(up to 32 Mbytes total)

❏

Four user-deﬁned I/O zones

— Address line forcing (to 0 or 1) for access to two

BIOS code and data sets

— Optional indirect addressing of memory

— XRD-XEN or XWR-XR/W mode support

— Supports both slow and fast devices

— For faster transactions in 16-bit data bus, strobe sig-

nals for address latches change automatically only

when the address is changed

Conﬁguration Control

— Compliant with PC01 Speciﬁcation Revision 1.0,

1999-2000

— Compliant with Hardware Design Guide Version 3.0

for Microsoft Windows 2000 Server, June 30 2000

— Plug and Play (PnP) Conﬁguration register structure

— Base Address strap, to setup the address of the

Index-Data register pair

— Flexible resource allocation for all logical devices:

❏

Relocatable base address

❏

15 IRQ routing options to serial IRQ

❏

Up to four optional 8-bit DMA channels

— SMBus control over pin multiplexing, module disable

and output TRI-STATE® for all Legacy modules

Legacy Modules

Serial Ports 1 and 2

— Software compatible with the 16550A and the 16450

— Supports shadow register for write-only bit monitoring

— UART data rates up to 1.5 Mbaud

— Three sets of Serial Interface pins

❏

Serial Interface 1

❏

Snoop or Take-over connection of Serial Inter-

face M

❏

Two-to-one multiplexing of Serial Ports 1 and 2 to

Serial Interface 2

Floppy Disk Controller (FDC)

— Programmable write protect

— Supports FM and MFM modes

— Supports Enhanced mode command for three-mode

Floppy Disk Drive (FDD)

— Perpendicular recording drive support for 2.88 MB

— Burst and Non-Burst modes

— Full support for IBM Tape Drive Register (TDR) im-

plementation of AT and PS/2 drive types

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