Revision 1.0

7

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1.3

PIN MULTIPLEXING

The table below shows only multiplexed pins, their associated functional blocks and the configuration bits for the selection

of the multiplexed options used in the PC87427.

Table 2. Pin Multiplexing Configuration

Pin

Functional

Block

Signal

Functional

Block

Signal

Functional

Block

Signal

Functional

Block

Signal

Configuration

Select

1

GPIO

GPIOE10

X-Bus

XA19_XD15

SIOCFC.XDATA16

2

GPIOE11

XA18_XD14

SIOCFC.XDATA16

3

GPIOE12

XA17_XD13

4

GPIOE13

XA16_XD12

5

GPIOE14

XA15_XD11

SIOCFC.XDATA16

6

GPIOE15

XA14_XD10

7

GPIOE16

XA13_XD9

FMC

FANOUT1

SIOCFC.XDATA16 &

SIOCFB.FANOUT1

8

GPIOE17

XA12_XD8

FANOUT2

SIOCFC.XDATA16 &

SIOCFB.FANOUT2

9

XRDY

FANIN7

SIOCF4.XRDYMUX

10

GPIO

GPIO06

XIRQ0

SIOCF5.XIRQ0MUX

13

GPIO07

Clocks

HFCKOUT

SIOCF4.HFCKMUX

14

GPIO20

X-Bus

XRD_XEN

SIOCF4.NOXBUS

15

GPIO21

XWR_XRW

16

GPIO22

XA3

17

GPIO23

XA2

18

GPO24

XA1

19

GPIO25

XA0_XA20

20

GPIOE46

SWC

SLPS3

SIOCF3.EXTSTMUX

21

GPIOE40

X-Bus

XA5

HMC

THRMTRIP1

SIOCF4.NOADDIR &

SIOCFB.TRIP1

22

GPIOE41

XA4

THRMTRIP2

SIOCF4.NOADDIR &

SIOCFB.TRIP2

24

GPIO30

XA11_XD7

SIOCF4.NOXBUS

25

GPIO31

XA10_XD6

26

GPIO32

XA9_XD5

27

GPIO33

XA8_XD4

28

GPIO34

XA7_XD3

29

GPIO35

XA6_XD2

30

GPIO36

XA5_XD1

31

GPIO37

XA4_XD0

32

GPIOE47

SWC

SLPS5

SIOCF3.EXTSTMUX

33

X-Bus

XSTB1

FMC

FANOUT2

SIOCF5.XSTB1MUX

34

XSTB0

Straps

XCNF0

35

XIRQ1

GPIO

GPIOE42

SWC

SLBTIN

SMBus

SMBALERT

SIOCF3.SLBTIMUX &

SIOCFC.XIRQ1MUX

36

XIRQ2

FMC

FANIN6

PWBTIN

SIOCF3.PWBTIMUX &

SIOCFB.FANIN6MUX

37

XA6

GPIO

GPIO27

SIOSMI

SIOCF3.SMIMUX &

SIOCF4.NOADDIR

38

GPIOE44

SIOSCI

SIOCF3.SCIMUX