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PC87427 Datasheet(PDF) 19 Page - National Semiconductor (TI) |
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PC87427 Datasheet(HTML) 19 Page - National Semiconductor (TI) |
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19 / 46 page ![]() 1.0 Signal/Pin Connection and Description (Continued) Revision 1.0 19 www.national.com RI1 101 VSB PU90 Pin can be left Not Connected RI2 102 VSB PU90 Pin can be left Not Connected General-Purpose Input/Output (GPIO) Ports GPIO00-04, 06-07 124-128, 10, 13 VSB or VDD PU30 Programmable GPIO05 82 VSB PU1K25 Programmable GPIOE10-15 1-6 VSB PU30 Programmable 109, 107-103 GPIOE16-17 7, 8 VSB PU30 Programmable GPIO20-27 14-19, 83, 37 VSB PU30 Programmable GPIO30-37 61-64, 74, 73-71 VSB PU30 Programmable GPIOE40-47 21-22, 35, 49, 38, 51, 20, 32 VSB PU30 Programmable GPIO50-57 85-87, 91-89, 80-79 VSB PU30 Programmable4 GPO60-63 54, 48, 45, 55 VSB PU30 Programmable Strap Configuration BADDR 100 VDD PU30 Strap5 TRIS 97 VDD PU30 Strap5 CKIN48 55 VSB PU30 Strap6 XCNF2-0 91, 108, 34 VSB PU30 Strap6 SMBSA 48 VSB PU30 Strap6 HFCKS 88 VSB PU30 Strap6 TEST 89 VDD PU30 Strap5 CTEST 52 VSB PU30 Strap6 1. Default at reset: disabled. 2. Default at reset: enabled. 3. Disabled when VDD is off. 4. Disabled during VSB Power-Up reset. 5. Active only during VDD Power-Up reset. 6. Active only during VSB Power-Up reset. Table 3. Internal Pull-Up and Pull-Down Resistors (Continued) Signal Pin(s) Power Well Type Comments |
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